1. Field of the Invention
The present invention relates to an on-chip failure analysis circuit and an on-chip failure analysis method, particularly to an on-chip failure analysis circuit of a semiconductor integrated circuit in which a self test circuit for a memory is built and an on-chip failure analysis method.
2. Related Art
There is well known a method for detecting failures in a production test, in which a built-in self test (hereinafter referred to as “BIST (Built-In Self Test)”) circuit is built in a semiconductor integrated circuit for embedded memories. Examples of the BIST circuit includes a comparator type BIST circuit which compares written data and read data to make a determination of the existence of a defect and a compressor type BIST circuit which compresses the read result in the BIST circuit to make the determination of the existence of the defect according to the compressed result.
There is also well known a repair technique of utilizing a memory cell having a redundant structure to repair the embedded memory determined as a defective memory. The memory cell having the redundant structure includes a spare row or a spare column. In the simplest case, the memory cell includes a set of spare rows or spare columns in each repair unit. In the more complicated case, the memory cell includes both the spare row and the spare column, the memory cell includes plural spare rows or spare columns, or one memory array is divided into plural segments each of which includes the memory cells having the repair structures.
In order to utilize the repair technique in the production of the semiconductor integrated circuit and the memory test, it is necessary to perform an analysis using the result of the memory test, to obtain a memory defect location and a spare used in repair (hereinafter referred to as “repair solution”), and to perform the redundancy allocation according to the obtained repair solution. Generally, the repair technique is realized as follows. That is, the memory test is performed using a memory tester and a direct access circuit which directly accesses the memory, a memory output map is written in a storage unit of the memory tester, and a program on the memory tester is started up to perform the analysis.
However, in the conventional repair technique, because the memory tester having a sufficiently large capacity of a storage unit is required to store pieces of fail data on all bits of the memory, it is necessary to use both the memory tester and a logic tester in the test for a system LSI (Large Scale Integration) including a logic circuit and the memory.
Because many embedded memories are provided on the usual large-scale system LSI, the direct access circuit is hardly prepared in each of all memories which become a repair object.
A built-in redundancy allocation (hereinafter referred to as “BIRA (Built-In Redundancy Allocation)” circuit which performs the analysis and redundancy allocation is well known as the technique of solving the problems (see Japanese Patent Application Laid-Open Publication No.2003-505814). The BIRA circuit is used along with the BIST circuit and obtains the repair solution by analyzing the fail data of the memory according to the failure detection result of the BIST circuit to output the obtained repair solution as the analysis result. In a production process of the semiconductor integrated circuit, a chip is repaired by programming a fuse device in which the analysis result is stored using a laser blow apparatus. In the case where the repair solution cannot be obtained, the BIRA circuit outputs the analysis result indicating that the repair solution cannot be obtained. In such cases, the analyzed chip is dealt with as a defective chip. The BIRA circuit can be realized by a relatively small-scale logic circuit for the minimum redundant structure having only one set of spare columns.
A document 1, “A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs”, International Test Conference, 2000, discloses a BIRA circuit. In the document 1, the BIRA circuit is used to repair the memory including plural spare rows and spare columns. In the document 1, the redundancy allocation is performed to all the possible repair solutions when the failure is detected in running the memory test, then a combination which successfully repairs the memory is adopted as an analysis result. Accordingly, in the document 1, a Content Addressable Memory (CAM), in which all the repair solutions are stored, is provided on the same integrated circuit.
However, in the BIRA circuit, because the number of repair solutions is increased as the numbers of spare columns and spare rows are increased, sometimes all the repair solutions cannot be stored in CAM. In the case where a new memory is provided for the purpose of the memory test, a hardware scale is enlarged, and disadvantageously the memory test needs to be run for the newly-provided memory.
On the other hand, a method for producing a complete fail bitmap of the memory is well known as the conventional memory analysis method.
However, in the conventional memory analysis method, it takes a long time to produce the complete fail bitmap in the case where information is collected in units of wafer or lot online during volume production. Particularly, the complete fail bitmap of the memory is not realistic when a logic tester and the BIST circuit are utilized.
On the other hand, in addition to the analysis for enhancing a production yield, there is well known a built-in self diagnosis (hereinafter referred to as “BISD (Built-In Self Diagnosis)” circuit which diagnoses the data used in the analysis. The BISD circuit makes a determination of a type of the memory failure such as a bit failure, row failure, column failure, or a combination thereof. A location of the defect is not always necessary for the BISD purpose.
A document 2, “Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process Monitoring”, International Test Conference, 2001, discloses a BISD circuit. In the document 2, fail data is compressed on the chip to produce a signature, the signature is output to the outside to be expanded and is reconstructed outside to make a determination of the type of the failure. In the document 2, because the data collection result is compressed, a data transfer time between the memory and the memory tester can be shortened to realize a type determination function for determining a type of the memory failure.
However, BISD circuit disclosed in the document 2, the type determination function depends on an external program, disadvantageously not only it takes a long time to analyze the memory like the conventional memory analysis, but also an information loss is generated due to the compression.